The present invention relates to a memory device having an improved arrangement of memory cells and including an improved decoder circuit, and more particularly to such a memory device employing n-type MOS transistors (MOSTs).
A conventional semiconductor memory employing n-type MOSTs, as described in "Digest of 1977 IEEE International Solid-State Circuit Conference", p.p. 12-13 includes two divided memory arrays, a column decoder arranged therebetween, and a row decoder for each memory array. First and second internal address signals from a common address buffer are time-sequentially supplied to the row and column decoders. The column decoder is coupled to the address buffer through a signal cutting MOST which is turned off and on respectively when the first and second internal address signals are applied to the column decoder. When a first external address signal is supplied to the address buffer, the first internal address signal corresponding to the first external address signal enables the row decoders. At this time, the above-mentioned signal cutting MOST is placed in the off-state, and therefore the first internal address signal is not applied to the column decoder. When the address buffer is subsequently applied with a second external address signal, the second internal address signal is delivered from the address buffer. At this time, the signal cutting MOST is placed in the on-state, and therefore the row and column decoders are enabled by the second internal address signal. In order to store the information or content of the first address signal in the row decoders, other signal cutting MOSTs are provided at the output sides of the row decoders, and these signal cutting MOSTs are turned off after each row decoder has been enabled by the first internal address signal. Thus, the row decoders deliver the first address signal information, and the column decoder delivers the second address signal information.
The conventional memory device having such construction, however, is not preferable from the standpoint of high speed operation, since the row and column decoders are both enabled by the second internal address signal, thereby increasing the load capacitance of the address buffer.
Further, in the case where, as described in U.S. Pat. No. 4,044,340, row lines are made of polysilicon and are finely patterned for selection of a large number of memory cells, the resistance of each row line is high. In order to reduce the propagation time of signal along the row line, it is desirable to increase the number of memory arrays. However, with the increased number of memory arrays row decoders must be provided at a correspondingly large number of locations. If the techniques described in the aforementioned reference are used intactly, a new wiring is required for applying the output signal of an address buffer to such a large number of row decoders, which lowers the integration degree in the memory device.